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authorRichard Zhu <hongxing.zhu@nxp.com>2025-10-15 11:04:18 +0800
committerShawn Guo <shawnguo@kernel.org>2025-11-12 09:51:28 +0800
commitdd93ee01a5056876be537b5bbb4a4a646b50982b (patch)
treebdec37fd914ffd4593c78d803820ad7dd1a8ddb5 /tools/perf/scripts/python/netdev-times.py
parent8f76686bbdc87035eefc56a700f6788ce84f0e26 (diff)
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arm64: dts: imx95-15x15-evk: Add supports-clkreq property to PCIe M.2 port
According to PCIe r6.1, sec 5.5.1. The following rules define how the L1.1 and L1.2 substates are entered: Both the Upstream and Downstream Ports must monitor the logical state of the CLKREQ# signal. Typical implement is using open drain, which connect RC's clkreq# to EP's clkreq# together and pull up clkreq#. imx95-15x15-evk matches this requirement, so add supports-clkreq to allow PCIe device enter ASPM L1 Sub-State. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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