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authorYixun Lan <dlan@gentoo.org>2025-11-01 20:56:42 +0800
committerYixun Lan <dlan@gentoo.org>2026-01-09 10:27:10 +0800
commitefe897b557e211a09f51d749eae5eca933e8bf56 (patch)
treed15fd15c53ba5cd6a3e381da2cbb4b03f14eda65 /tools/perf/scripts/python/parallel-perf.py
parent092c2353f9ba42a3c534bccf91ea7af5b6e9bb23 (diff)
downloadlinux-efe897b557e211a09f51d749eae5eca933e8bf56.tar.gz
linux-efe897b557e211a09f51d749eae5eca933e8bf56.zip
dt-bindings: soc: spacemit: k3: add clock support
Add compatible strings for clock drivers to support Spacemit K3 SoC, also includes all the defined clock IDs. The SpacemiT K3 SoC clock IP is scattered over several different blocks, which are APBC, APBS, APMU, DCIU, MPMU, all of them are capable of generating clock and reset signals. APMU and MPMU have additional Power Domain management functionality. Following is a brief list that shows devices managed in each block: APBC: UART, GPIO, PWM, SPI, TIMER, I2S, IR, DR, TSEN, IPC, CAN APBS: various PPL clocks control APMU: CCI, CPU, CSI, ISP, LCD, USB, QSPI, DMA, VPU, GPU, DSI, PCIe, EMAC.. DCID: SRAM, DMA, TCM MPMU: various PLL1 derived clocks, UART, WATCHDOG, I2S Link: https://lore.kernel.org/r/20260108-k3-clk-v5-1-42a11b74ad58@gentoo.org Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Yixun Lan <dlan@gentoo.org>
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