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| author | Sean Christopherson <seanjc@google.com> | 2026-01-08 19:45:32 -0800 |
|---|---|---|
| committer | Sean Christopherson <seanjc@google.com> | 2026-01-13 17:35:32 -0800 |
| commit | 000d75b0b18622e7454c3955631a3cf39e0353e7 (patch) | |
| tree | 54c0434a8a1cdbd9de586ff593f8c56001656f75 /tools/perf/scripts/python/stackcollapse.py | |
| parent | 249cc1ab4b9a5caa63d7e9c5a5b7862046089dd4 (diff) | |
| download | linux-000d75b0b18622e7454c3955631a3cf39e0353e7.tar.gz linux-000d75b0b18622e7454c3955631a3cf39e0353e7.zip | |
KVM: x86: Update APICv ISR (a.k.a. SVI) as part of kvm_apic_update_apicv()
Fold the calls to .hwapic_isr_update() in kvm_apic_set_state(),
kvm_lapic_reset(), and __kvm_vcpu_update_apicv() into
kvm_apic_update_apicv(), as updating SVI is directly related to updating
KVM's own cache of ISR information, e.g. SVI is more or less the APICv
equivalent of highest_isr_cache.
Note, calling .hwapic_isr_update() during kvm_apic_update_apicv() has
benign side effects, as doing so changes the orders of the calls in
kvm_lapic_reset() and kvm_apic_set_state(), specifically with respect to
to the order between .hwapic_isr_update() and .apicv_post_state_restore().
However, the changes in ordering are glorified nops as the former hook is
VMX-only and the latter is SVM-only.
Reviewed-by: Chao Gao <chao.gao@intel.com>
Link: https://patch.msgid.link/20260109034532.1012993-9-seanjc@google.com
Signed-off-by: Sean Christopherson <seanjc@google.com>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions
