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| author | Dan Williams <dan.j.williams@intel.com> | 2021-08-02 10:29:49 -0700 |
|---|---|---|
| committer | Dan Williams <dan.j.williams@intel.com> | 2021-08-06 08:22:53 -0700 |
| commit | 06737cd0d216be1cf6e8052e4fca0d391298f184 (patch) | |
| tree | 76c8172133fa52148d271c10d238a8b503089292 /tools/perf/scripts/python/stackcollapse.py | |
| parent | cxl/core: Improve CXL core kernel docs (diff) | |
| download | linux-06737cd0d216be1cf6e8052e4fca0d391298f184.tar.gz linux-06737cd0d216be1cf6e8052e4fca0d391298f184.zip | |
cxl/core: Move pmem functionality
Refactor the pmem / nvdimm-bridge functionality from core/bus.c to
core/pmem.c. Introduce drivers/core/core.h to communicate data
structures and helpers between the core bus and other functionality that
registers devices on the bus.
Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Link: https://lore.kernel.org/r/162792538899.368511.3881663908293411300.stgit@dwillia2-desk3.amr.corp.intel.com
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions