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| author | Sowjanya Komatineni <skomatineni@nvidia.com> | 2019-08-16 12:41:59 -0700 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2019-11-11 14:53:04 +0100 |
| commit | 3214be6cb1e487b0f8c3bb2eac9b06df07a07e06 (patch) | |
| tree | 3fef03b90fb25aea7712216e24b5843ea6006ca1 /tools/perf/scripts/python/stackcollapse.py | |
| parent | clk: tegra: Use fence_udelay() during PLLU init (diff) | |
| download | linux-3214be6cb1e487b0f8c3bb2eac9b06df07a07e06.tar.gz linux-3214be6cb1e487b0f8c3bb2eac9b06df07a07e06.zip | |
clk: tegra: Share clk and rst register defines with Tegra clock driver
Move CLK_OUT_ENB and RST_DEVICES registers to clk.h to share these with
Tegra clock driver.
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions