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| author | Imre Deak <imre.deak@intel.com> | 2025-11-20 19:23:54 +0200 |
|---|---|---|
| committer | Imre Deak <imre.deak@intel.com> | 2025-11-21 20:50:30 +0200 |
| commit | 370f45b1cea859484691128ec205abc7e9402fb7 (patch) | |
| tree | 75a5c460d5a336f4b5230ea9512ccfe3461a5c26 /tools/perf/scripts/python/stackcollapse.py | |
| parent | a5f0cc8e0cd4007370af6985cb152001310cf20c (diff) | |
| download | linux-370f45b1cea859484691128ec205abc7e9402fb7.tar.gz linux-370f45b1cea859484691128ec205abc7e9402fb7.zip | |
drm/i915/cx0: Fix port to PLL ID mapping on BMG
The intel_port_to_tc() call in mtl_port_to_pll_id() assumed that all
TypeC DDI ports are connected to a TypeC PHY. This is not true on BMG
where all the ports - including the PORT_TC1..4 TypeC DDI ports - are
connected to a non-TypeC PHY. For these ports intel_port_to_tc()
returns TC_PORT_NONE, which results in an incorrect port -> PLL ID
mapping. Fix this up by using the expected PORT_TC1..4 port ->
TC_PORT_1..4 tc_port mapping on BMG as well.
Fixes: ca1eda5cd476c ("drm/i915/cx0: Add MTL+ .get_dplls hook")
Cc: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Link: https://patch.msgid.link/20251120172358.1282765-1-imre.deak@intel.com
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions