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| author | Daniel Baluta <daniel.baluta@nxp.com> | 2019-08-06 18:12:10 +0300 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2019-08-07 14:26:03 +0100 |
| commit | 5f0ac20ed6db1d6da2eea8b862cf3d54fdfb5830 (patch) | |
| tree | 377f932bc231bbb6166d99f3771fea031987eb36 /tools/perf/scripts/python/stackcollapse.py | |
| parent | abf31feea26c0f412a191c83f408311a0de7435c (diff) | |
| download | linux-5f0ac20ed6db1d6da2eea8b862cf3d54fdfb5830.tar.gz linux-5f0ac20ed6db1d6da2eea8b862cf3d54fdfb5830.zip | |
ASoC: fsl_sai: Add registers definition for multiple datalines
SAI IP supports up to 8 data lines. The configuration of
supported number of data lines is decided at SoC integration
time.
This patch adds definitions for all related data TX/RX registers:
* TDR0..7, Transmit data register
* TFR0..7, Transmit FIFO register
* RDR0..7, Receive data register
* RFR0..7, Receive FIFO register
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
Acked-by: Nicolin Chen <nicoleotsuka@gmail.com>
Link: https://lore.kernel.org/r/20190806151214.6783-2-daniel.baluta@nxp.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions