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| author | Manasi Navare <manasi.d.navare@intel.com> | 2018-11-28 12:26:18 -0800 |
|---|---|---|
| committer | Manasi Navare <manasi.d.navare@intel.com> | 2018-11-29 12:23:54 -0800 |
| commit | 91ba2c8be4b7eef3c9c424ddd862cdb302f252f3 (patch) | |
| tree | d005748c1067698b8f041873ae8dfa633ed64338 /tools/perf/scripts/python/stackcollapse.py | |
| parent | drm/i915/dp: Enable/Disable DSC in DP Sink (diff) | |
| download | linux-91ba2c8be4b7eef3c9c424ddd862cdb302f252f3.tar.gz linux-91ba2c8be4b7eef3c9c424ddd862cdb302f252f3.zip | |
drm/i915/dsc: Add a power domain for VDSC on eDP/MIPI DSI
On Icelake, a separate power well PG2 is created for
VDSC engine used for eDP/MIPI DSI. This patch adds a new
display power domain for Power well 2.
v3:
* Call it POWER_DOMAIN_TRANSCODER_EDP_VDSC (Ville)
* Move it around TRANSCODER power domain defs (Ville)
v2:
* Fix the power well mismatch CI error (Ville)
* Rename as VDSC_PIPE_A (Imre)
* Fix a whitespace (Anusha)
* Fix Comments (Imre)
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Reviewed-by: Ville Syrjala <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181128202628.20238-7-manasi.d.navare@intel.com
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions