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| author | Duncan Ma <duncan.ma@amd.com> | 2022-08-15 17:37:32 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2022-08-30 16:59:55 -0400 |
| commit | d1b4a51a4ca8954f30cf4671b25c4f8637c45600 (patch) | |
| tree | 2cfc07adfe7d37885db234512f83b1989dfc8145 /tools/perf/scripts/python/stackcollapse.py | |
| parent | drm/amd/display: Fix DCN32 DPSTREAMCLK_CNTL programming (diff) | |
| download | linux-d1b4a51a4ca8954f30cf4671b25c4f8637c45600.tar.gz linux-d1b4a51a4ca8954f30cf4671b25c4f8637c45600.zip | |
drm/amd/display: Fix OTG H timing reset for dcn314
[Why]
When ODM is enabled, H timing control register reset
to 0. Div mode manual field get overwritten causing
no display on certain modes for dcn314.
[How]
Use REG_UPDATE instead of REG_SET to set div_mode
field.
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Brian Chang <Brian.Chang@amd.com>
Signed-off-by: Duncan Ma <duncan.ma@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions