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| author | Cristian Ciocaltea <cristian.ciocaltea@collabora.com> | 2025-02-04 14:40:08 +0200 |
|---|---|---|
| committer | Heiko Stuebner <heiko@sntech.de> | 2025-02-06 12:01:34 +0100 |
| commit | eb4262203d7d85eb7b6f2696816db272e41f5464 (patch) | |
| tree | dc4dd81dbd65d04bbe71e3a4bd2e99f4b196bac4 /tools/perf/scripts/python/syscall-counts.py | |
| parent | arm64: dts: rockchip: Enable HDMI0 PHY clk provider on RK3588 (diff) | |
| download | linux-eb4262203d7d85eb7b6f2696816db272e41f5464.tar.gz linux-eb4262203d7d85eb7b6f2696816db272e41f5464.zip | |
arm64: dts: rockchip: Add HDMI0 PHY PLL clock source to VOP2 on RK3588
VOP2 on RK3588 is able to use the HDMI PHY PLL as an alternative and
more accurate pixel clock source to improve handling of display modes up
to 4K@60Hz on video ports 0, 1 and 2.
For now only HDMI0 output is supported, hence add the related PLL clock.
Tested-by: FUKAUMI Naoki <naoki@radxa.com>
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Link: https://lore.kernel.org/r/20250204-vop2-hdmi0-disp-modes-v3-5-d71c6a196e58@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'tools/perf/scripts/python/syscall-counts.py')
0 files changed, 0 insertions, 0 deletions