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| author | Konrad Dybcio <quic_kdybcio@quicinc.com> | 2024-09-19 00:57:22 +0200 |
|---|---|---|
| committer | Bjorn Andersson <andersson@kernel.org> | 2024-10-05 21:52:56 -0500 |
| commit | 051ff563cb3d87c631c8997d9b3636a7b59a12b9 (patch) | |
| tree | acd8027ce9048d33a16bcd58042213df3a0c28c1 /tools/perf/scripts/python/task-analyzer.py | |
| parent | arm64: dts: qcom: sm8150: Affirm IDR0.CCTW on apps_smmu (diff) | |
| download | linux-051ff563cb3d87c631c8997d9b3636a7b59a12b9.tar.gz linux-051ff563cb3d87c631c8997d9b3636a7b59a12b9.zip | |
arm64: dts: qcom: sm8350: Affirm IDR0.CCTW on apps_smmu
On RPMh-based SoCs, the APPS SMMU advertizes support for cache-coherent
pagetable walk via the IDR0 register. This however is not respected by
the arm-smmu driver unless dma-coherent is set.
Mark the node as dma-coherent to ensure this (and other) implementations
take this coherency into account.
Signed-off-by: Konrad Dybcio <quic_kdybcio@quicinc.com>
Tested-by: Steev Klimaszewski <steev@kali.org> # Thinkpad X13s (sc8280xp)
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on sdm845-rb3
Link: https://lore.kernel.org/r/20240919-topic-apps_smmu_coherent-v1-9-5b3a8662403d@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/task-analyzer.py')
0 files changed, 0 insertions, 0 deletions