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| author | Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> | 2025-11-19 16:35:21 +0200 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2026-01-05 14:37:17 +0100 |
| commit | 1a66160fb28abcd228f69e00bb183a4749f23805 (patch) | |
| tree | dc243b85ebec8dda2f7d352bb664ac10b914e2c4 /tools/perf/scripts/python/task-analyzer.py | |
| parent | 40a4c75e7f7170f4dc9f077ae480fe5775a780a1 (diff) | |
| download | linux-1a66160fb28abcd228f69e00bb183a4749f23805.tar.gz linux-1a66160fb28abcd228f69e00bb183a4749f23805.zip | |
arm64: dts: renesas: rzg3s-smarc-som: Add PCIe reference clock
Versa3 clock generator available on RZ/G3S SMARC Module provides the
reference clock for SoC PCIe interface. Update the device tree to reflect
this connection.
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Acked-by: Manivannan Sadhasivam <mani@kernel.org>
Link: https://patch.msgid.link/20251119143523.977085-5-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/perf/scripts/python/task-analyzer.py')
0 files changed, 0 insertions, 0 deletions