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| author | Jean-Baptiste Maneyrol <jean-baptiste.maneyrol@tdk.com> | 2024-06-07 08:10:39 +0000 |
|---|---|---|
| committer | Jonathan Cameron <Jonathan.Cameron@huawei.com> | 2024-06-13 19:19:24 +0100 |
| commit | 50cfe81b71e50d7a7f6afb84d5dbe084ed4ea174 (patch) | |
| tree | e5c18a0f4b094e5cb90b39c3ee612211701448b1 /tools/perf/scripts/python/task-analyzer.py | |
| parent | iio: adc: mcp3564: drop redundant open-coded spi_get_device_match_data() (diff) | |
| download | linux-50cfe81b71e50d7a7f6afb84d5dbe084ed4ea174.tar.gz linux-50cfe81b71e50d7a7f6afb84d5dbe084ed4ea174.zip | |
iio: imu: inv_icm42600: add register caching in the regmap
Register caching is improving bus access a lot because of the register
window bank setting. Previously, bank register was set for every
register access. Now with caching, it happens only when changing bank
which is very infrequent.
Signed-off-by: Jean-Baptiste Maneyrol <jean-baptiste.maneyrol@tdk.com>
Link: https://lore.kernel.org/r/20240607081039.789079-1-inv.git-commit@tdk.com
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Diffstat (limited to 'tools/perf/scripts/python/task-analyzer.py')
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