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| author | Imre Deak <imre.deak@intel.com> | 2025-11-20 19:23:57 +0200 |
|---|---|---|
| committer | Imre Deak <imre.deak@intel.com> | 2025-11-21 20:51:35 +0200 |
| commit | dc5b3ef88ba7cc9f2748b75b6b127b2b400315cc (patch) | |
| tree | d3b7f50b9ac84acf1ba70d56cf02bc190f4179dd /tools/perf/scripts/python/task-analyzer.py | |
| parent | 07ba4ecfd111cb56464faf6ada9937b4e18fac23 (diff) | |
| download | linux-dc5b3ef88ba7cc9f2748b75b6b127b2b400315cc.tar.gz linux-dc5b3ef88ba7cc9f2748b75b6b127b2b400315cc.zip | |
drm/i915/cx0: Read out power-down state of both TXs in PHY lane 0
If the number of used lanes is 1 or 2 then the power-down state of both
TX lanes in PHY lane 0 should be read out. If 1 lane is used only 1 TX
lane will be checked, make sure both TXs are checked in this case.
Cc: Mika Kahola <mika.kahola@intel.com>
Cc: Suraj Kandpal <suraj.kandpal@intel.com>
Fixes: 230d4c748113 ("drm/i915/cx0: Track the Cx0 PHY enabled lane count in the PLL state")
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Link: https://patch.msgid.link/20251120172358.1282765-4-imre.deak@intel.com
Diffstat (limited to 'tools/perf/scripts/python/task-analyzer.py')
0 files changed, 0 insertions, 0 deletions