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| author | Yixun Lan <yixun.lan@amlogic.com> | 2017-12-15 22:17:41 +0800 |
|---|---|---|
| committer | Kevin Hilman <khilman@baylibre.com> | 2018-01-05 15:27:30 -0800 |
| commit | 06b7a631878a71439235aa45b531c0e7b81241a7 (patch) | |
| tree | b8453a7add567f8a8d316cbac4b07e7804201c1d /tools/perf/scripts/python | |
| parent | Merge tag 'meson-clk-headers-for-v4.16-2' of git://github.com/BayLibre/clk-me... (diff) | |
| download | linux-06b7a631878a71439235aa45b531c0e7b81241a7.tar.gz linux-06b7a631878a71439235aa45b531c0e7b81241a7.zip | |
arm64: dts: meson-axg: switch uart_ao clock to CLK81
Switch the uart_ao pclk to CLK81 since the clock driver is ready.
Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions