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| author | Matt Roper <matthew.d.roper@intel.com> | 2015-03-18 15:04:47 -0700 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2015-03-20 11:48:22 +0100 |
| commit | 08fd59fcc8c0f9732214fb93ad5cb09f67cb1124 (patch) | |
| tree | 8bc245df2caf0f086a4780180d6ba3863f38e9d1 /tools/perf/scripts/python | |
| parent | drm/i915/chv: use vlv_PLL_is_optimal in chv_find_best_dpll (diff) | |
| download | linux-08fd59fcc8c0f9732214fb93ad5cb09f67cb1124.tar.gz linux-08fd59fcc8c0f9732214fb93ad5cb09f67cb1124.zip | |
drm/i915: Move vblank wait determination to 'check' phase
Determining whether we'll need to wait for vblanks is something we
should determine during the atomic 'check' phase, not the 'commit'
phase. Note that we only set these bits in the branch of 'check' where
intel_crtc->active is true so that we don't try to wait on a disabled
CRTC.
The whole 'wait for vblank after update' flag should go away in the
future, once we start handling watermarks in a proper atomic manner.
This regression has been introduced in
commit 2fdd7def16dd7580f297827930126c16b152ec11
Author: Matt Roper <matthew.d.roper@intel.com>
Date: Wed Mar 4 10:49:04 2015 -0800
drm/i915: Don't clobber plane state on internal disables
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Root-cause-analysis-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89550
Testcase: igt/pm_rpm/legacy-planes
Testcase: igt/pm_rpm/legacy-planes-dpms
Testcase: igt/pm_rpm/universal-planes
Testcase: igt/pm_rpm/universal-planes-dpms
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Tested-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions