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| author | Marc Zyngier <marc.zyngier@arm.com> | 2017-12-03 17:50:00 +0000 |
|---|---|---|
| committer | Marc Zyngier <marc.zyngier@arm.com> | 2018-03-19 13:05:13 +0000 |
| commit | 11d764079c9f25d1da8e10906d54da7fefec5844 (patch) | |
| tree | 02f756085f8258d087dc0ae1c4196933dc7e2f8a /tools/perf/scripts/python | |
| parent | arm64; insn: Add encoder for the EXTR instruction (diff) | |
| download | linux-11d764079c9f25d1da8e10906d54da7fefec5844.tar.gz linux-11d764079c9f25d1da8e10906d54da7fefec5844.zip | |
arm64: insn: Allow ADD/SUB (immediate) with LSL #12
The encoder for ADD/SUB (immediate) can only cope with 12bit
immediates, while there is an encoding for a 12bit immediate shifted
by 12 bits to the left.
Let's fix this small oversight by allowing the LSL_12 bit to be set.
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions