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| author | Chen-Yu Tsai <wens@csie.org> | 2017-05-19 15:06:08 +0800 |
|---|---|---|
| committer | Maxime Ripard <maxime.ripard@free-electrons.com> | 2017-06-07 15:32:15 +0200 |
| commit | 13e0dde8b2ed043aa3e65437342d501715d975c1 (patch) | |
| tree | ebc8e171a82bb4743fbcc27de067fcf79a261046 /tools/perf/scripts/python | |
| parent | dt-bindings: clock: sunxi-ccu: Add compatible string for A83T CCU (diff) | |
| download | linux-13e0dde8b2ed043aa3e65437342d501715d975c1.tar.gz linux-13e0dde8b2ed043aa3e65437342d501715d975c1.zip | |
clk: sunxi-ng: Support multiple variable pre-dividers
On the A83T, the AHB1 clock has a shared pre-divider on the two
PLL-PERIPH clock parents. To support such instances of shared
pre-dividers, this patch extends the mux clock type to support
multiple variable pre-dividers.
As the pre-dividers are only used to calculate the rate, but
do not participate in the factorization process, this is fairly
straightforward.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions