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| author | Will Deacon <will.deacon@arm.com> | 2017-03-10 20:32:22 +0000 |
|---|---|---|
| committer | Catalin Marinas <catalin.marinas@arm.com> | 2017-03-20 16:16:57 +0000 |
| commit | 155433cb365ee4666bdf7c3c7bc2978b17be36a4 (patch) | |
| tree | 43668ce6b2cfffb1327fe5c1054ddc228a108f1a /tools/perf/scripts/python | |
| parent | arm64: cacheinfo: Remove CCSIDR-based cache information probing (diff) | |
| download | linux-155433cb365ee4666bdf7c3c7bc2978b17be36a4.tar.gz linux-155433cb365ee4666bdf7c3c7bc2978b17be36a4.zip | |
arm64: cache: Remove support for ASID-tagged VIVT I-caches
As a recent change to ARMv8, ASID-tagged VIVT I-caches are removed
retrospectively from the architecture. Consequently, we don't need to
support them in Linux either.
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions