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| author | Dinh Nguyen <dinguyen@opensource.altera.com> | 2015-07-24 22:10:59 -0500 |
|---|---|---|
| committer | Dinh Nguyen <dinguyen@opensource.altera.com> | 2015-07-24 22:10:59 -0500 |
| commit | 2e4c7588f6c1d24ae991a85140e05139e953c9b5 (patch) | |
| tree | 4630e475907f5f564d00f3453c27cf0c786bf7a0 /tools/perf/scripts/python | |
| parent | ARM: socfpga: dts: add missing clock gates to socfpga.dtsi (diff) | |
| download | linux-2e4c7588f6c1d24ae991a85140e05139e953c9b5.tar.gz linux-2e4c7588f6c1d24ae991a85140e05139e953c9b5.zip | |
ARM: socfpga: dts: add osc1 as a possible parent for dbg_base_clk
The dbg_base_clk can also have osc1 has a parent.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions