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| author | Suzuki K Poulose <suzuki.poulose@arm.com> | 2018-07-04 23:07:46 +0100 |
|---|---|---|
| committer | Will Deacon <will.deacon@arm.com> | 2018-07-05 10:20:59 +0100 |
| commit | 314d53d297980676011e6fd83dac60db4a01dc70 (patch) | |
| tree | 201eddf7774afbd9ef20845a69f091aeef94e056 /tools/perf/scripts/python | |
| parent | arm64: Fix mismatched cache line size detection (diff) | |
| download | linux-314d53d297980676011e6fd83dac60db4a01dc70.tar.gz linux-314d53d297980676011e6fd83dac60db4a01dc70.zip | |
arm64: Handle mismatched cache type
Track mismatches in the cache type register (CTR_EL0), other
than the D/I min line sizes and trap user accesses if there are any.
Fixes: be68a8aaf925 ("arm64: cpufeature: Fix CTR_EL0 field definitions")
Cc: <stable@vger.kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions