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| author | Paul Hsieh <Paul.Hsieh@amd.com> | 2023-03-22 17:46:31 +0800 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2023-04-11 18:03:35 -0400 |
| commit | 385c3e4c29e1d4ce8f68687a8c84621e4c0e0416 (patch) | |
| tree | 953755c724763a3a78c5310b818846be3a3ea141 /tools/perf/scripts/python | |
| parent | drm/amd/display: prep work for root clock optimization enablement for DCN314 (diff) | |
| download | linux-385c3e4c29e1d4ce8f68687a8c84621e4c0e0416.tar.gz linux-385c3e4c29e1d4ce8f68687a8c84621e4c0e0416.zip | |
drm/amd/display: Correct DML calculation to follow HW SPEC
[Why]
In 2560x1600@240p eDP panel, driver use lowest voltage level
to play 1080p video cause underflow. According to HW SPEC,
the senario should use high voltage level.
[How]
ChromaPre value is zero when bandwidth validation.
Correct ChromaPre calculation.
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Paul Hsieh <Paul.Hsieh@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions