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| author | Jouni Högander <jouni.hogander@intel.com> | 2025-02-13 08:47:55 +0200 |
|---|---|---|
| committer | Jouni Högander <jouni.hogander@intel.com> | 2025-02-13 16:41:22 +0200 |
| commit | 3b5bf853e3093eec34dc080ab375c2bd0758995d (patch) | |
| tree | 2a45a2953088b1018d1b3cb57be846e85e6000da /tools/perf/scripts/python | |
| parent | drm/i915/psr: Split setting sff and cff bits away from intel_psr_force_update (diff) | |
| download | linux-3b5bf853e3093eec34dc080ab375c2bd0758995d.tar.gz linux-3b5bf853e3093eec34dc080ab375c2bd0758995d.zip | |
drm/i915/psr: Add register definitions for SFF_CTL and CFF_CTL registers
Add register definitions for SFF_CTL and CFF_CTL registers. Name them as
LNL_SFF_CTL and LNL_CFF_CTL.
v2: use _MMIO_TRANS instead of _MMIO_TRANS2
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Animesh Manna <animesh.manna@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250213064804.2077127-5-jouni.hogander@intel.com
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions