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| author | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2018-10-25 17:56:36 -0700 |
|---|---|---|
| committer | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2018-10-29 10:44:16 -0700 |
| commit | 42882336e62aab00278114392a16374f272a0c99 (patch) | |
| tree | b76874df914d0b32009d56ef21d09462c7da93e5 /tools/perf/scripts/python | |
| parent | drm/i915: Kill GEN_FOREVER (diff) | |
| download | linux-42882336e62aab00278114392a16374f272a0c99.tar.gz linux-42882336e62aab00278114392a16374f272a0c99.zip | |
drm/i915/glk: Remove 99% limitation.
While checking the opportunity to add a display_gen
check to allow glk and cnl to be on same bucket I noticed
these FIXME cases here.
So I got the confirmation from HW architect that we actually
never needed this workaround.
"GLK supports 2 pixel per clock, so pixel clock can be up to 2 * cdclk."
So, this reverts commit 97f55ca5b662 ("drm/i915/glk: limit pixel
clock to 99% of cdclk workaround")
Fixes: 97f55ca5b662 ("drm/i915/glk: limit pixel clock to 99% of cdclk workaround")
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Madhav Chauhan <madhav.chauhan@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Clinton Taylor <clinton.a.taylor@intel.com>
Cc: Arthur J Runyan <arthur.j.runyan@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181026005636.22274-1-rodrigo.vivi@intel.com
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions