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authorZhanjun Dong <zhanjun.dong@intel.com>2023-07-06 10:47:04 -0700
committerDaniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>2023-07-12 09:27:43 -0700
commit43aa755eae2cda71684f3f5fe40c00f728d25722 (patch)
tree075846e68cb80f7bfc8a0e6f2a224241e7b51321 /tools/perf/scripts/python
parentdrm/i915/perf: add sentinel to xehp_oa_b_counters (diff)
downloadlinux-43aa755eae2cda71684f3f5fe40c00f728d25722.tar.gz
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drm/i915/mtl: Update cache coherency setting for context structure
As context structure is shared memory for CPU/GPU, Wa_22016122933 is needed for this memory block as well. Signed-off-by: Zhanjun Dong <zhanjun.dong@intel.com> CC: Fei Yang <fei.yang@intel.com> Reviewed-by: Fei Yang <fei.yang@intel.com> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230706174704.177929-1-zhanjun.dong@intel.com
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