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| author | Rohit Khaire <rohit.khaire@amd.com> | 2021-06-04 12:45:50 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2021-06-04 16:02:57 -0400 |
| commit | 46ed43e67df6648c421504146d5bd020dd0de4eb (patch) | |
| tree | 0e4fb05f444df7c87084231ba845c0fda194977b /tools/perf/scripts/python | |
| parent | drm/amdgpu: Enable RLCG read/write interface for Sienna Cichlid (diff) | |
| download | linux-46ed43e67df6648c421504146d5bd020dd0de4eb.tar.gz linux-46ed43e67df6648c421504146d5bd020dd0de4eb.zip | |
drm/amdgpu: Modify GC register access to use _SOC15 macros
In SRIOV environment, KMD should access GC registers
with RLCG if GC indirect access flag enabled.
Using _SOC15 read/write macros ensures that they go
through RLC when flag is enabled.
Signed-off-by: Rohit Khaire <rohit.khaire@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions