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| author | Nicolin Chen <Guangyu.Chen@freescale.com> | 2014-05-06 16:56:00 +0800 |
|---|---|---|
| committer | Mark Brown <broonie@linaro.org> | 2014-05-12 23:13:13 +0100 |
| commit | 57ebbcafab0ce8cce4493c6a243ecdd7066e6ef1 (patch) | |
| tree | f1c3fc761b5e43b85d319f580f9f04991125154d /tools/perf/scripts/python | |
| parent | ASoC: fsl_esai: Fix incorrect condition within ratio range check for FP (diff) | |
| download | linux-57ebbcafab0ce8cce4493c6a243ecdd7066e6ef1.tar.gz linux-57ebbcafab0ce8cce4493c6a243ecdd7066e6ef1.zip | |
ASoC: fsl_esai: Only bypass sck_div for EXTAL source
ESAI can only output EXTAL clock source directly. But for FSYS clock source,
ESAI can not output it without getting through PSR PM dividers.
So this patch adds an extra check in the code.
Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions