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| author | Andrew Jiang <Andrew.Jiang@amd.com> | 2017-10-10 14:36:39 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2017-10-21 16:51:08 -0400 |
| commit | 58bb0e63dd99c4bdb84e79a95311bb6899789681 (patch) | |
| tree | 58ebcc0b46fffdaec003ed58a4387ca2ff879067 /tools/perf/scripts/python | |
| parent | drm/amd/display: check SR_WATERMARK regs prior to write (diff) | |
| download | linux-58bb0e63dd99c4bdb84e79a95311bb6899789681.tar.gz linux-58bb0e63dd99c4bdb84e79a95311bb6899789681.zip | |
drm/amd/display: Correct timings in build scaling params
A previous patch set the addressable timing as active + border,
when in fact, the VESA standard specifies active as equal to
addressable + border.
This patch makes the fix more correct and in line with the standard.
Signed-off-by: Andrew Jiang <Andrew.Jiang@amd.com>
Reviewed-by: Andrew Jiang <Andrew.Jiang@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions