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| author | Radim Krčmář <rkrcmar@redhat.com> | 2017-10-06 19:25:54 +0200 |
|---|---|---|
| committer | Paolo Bonzini <pbonzini@redhat.com> | 2017-10-12 14:01:54 +0200 |
| commit | 5d74a6999368ad1991491b1913bb80faf1925e67 (patch) | |
| tree | 11d7b1be0a3810b03ecf7dd66374194194239255 /tools/perf/scripts/python | |
| parent | KVM: x86: handle 0 write to TSC_DEADLINE MSR (diff) | |
| download | linux-5d74a6999368ad1991491b1913bb80faf1925e67.tar.gz linux-5d74a6999368ad1991491b1913bb80faf1925e67.zip | |
KVM: x86: really disarm lapic timer when clearing TMICT
preemption timer only looks at tscdeadline and could inject already
disarmed timer.
Signed-off-by: Radim Krčmář <rkrcmar@redhat.com>
Reviewed-by: Wanpeng Li <wanpeng.li@hotmail.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions