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| author | Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> | 2015-09-10 04:55:46 -0300 |
|---|---|---|
| committer | Mauro Carvalho Chehab <mchehab@osg.samsung.com> | 2016-02-19 09:11:34 -0200 |
| commit | 5dc1e5fb47cd7433130fc496d426de45decead15 (patch) | |
| tree | 9d7bdf29a646ddc7da55d5a292165707162dc96a /tools/perf/scripts/python | |
| parent | [media] v4l: vsp1: Document the vsp1_pipeline structure (diff) | |
| download | linux-5dc1e5fb47cd7433130fc496d426de45decead15.tar.gz linux-5dc1e5fb47cd7433130fc496d426de45decead15.zip | |
[media] v4l: vsp1: Fix typo in VI6_DISP_IRQ_STA_DST register bit name
Rename the VI6_DISP_IRQ_STA_DSE register bit to VI6_DISP_IRQ_STA_DST to
fix a typo and match the datasheet.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@osg.samsung.com>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions