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| author | Will Deacon <will.deacon@arm.com> | 2018-06-14 11:23:38 +0100 |
|---|---|---|
| committer | Will Deacon <will.deacon@arm.com> | 2018-12-06 16:47:05 +0000 |
| commit | 679db70801da9fda91d26caf13bf5b5ccc74e8e8 (patch) | |
| tree | 99b7df12e3d5dbdb4d14cd0fe317b643ee7a1444 /tools/perf/scripts/python | |
| parent | arm64: Add support for SB barrier and patch in over DSB; ISB sequences (diff) | |
| download | linux-679db70801da9fda91d26caf13bf5b5ccc74e8e8.tar.gz linux-679db70801da9fda91d26caf13bf5b5ccc74e8e8.zip | |
arm64: entry: Place an SB sequence following an ERET instruction
Some CPUs can speculate past an ERET instruction and potentially perform
speculative accesses to memory before processing the exception return.
Since the register state is often controlled by a lower privilege level
at the point of an ERET, this could potentially be used as part of a
side-channel attack.
This patch emits an SB sequence after each ERET so that speculation is
held up on exception return.
Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions