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| author | Krzysztof Adamski <k@japko.eu> | 2016-02-22 14:03:25 +0100 |
|---|---|---|
| committer | Maxime Ripard <maxime.ripard@free-electrons.com> | 2016-02-25 11:30:32 -0800 |
| commit | 6e17b4181603d183d20c73f4535529ddf2a2a020 (patch) | |
| tree | a955d26015816ed7e2d23937fe1e4bb731fd4908 /tools/perf/scripts/python | |
| parent | clk: sunxi: Improve divs_clk error handling and reporting (diff) | |
| download | linux-6e17b4181603d183d20c73f4535529ddf2a2a020.tar.gz linux-6e17b4181603d183d20c73f4535529ddf2a2a020.zip | |
clk: sunxi: Add apb0 gates for H3
This patch adds support for APB0 in H3. It seems to be compatible with
earlier SOCs. apb0 gates controls R_ block peripherals (R_PIO, R_IR,
etc).
Since this gates behave just like any Allwinner clock gate, add a generic
compatible that can be reused if we don't have any clock to protect.
Signed-off-by: Krzysztof Adamski <k@japko.eu>
[Maxime: Removed the H3 compatible from the simple-gates driver, reworked
the commit log a bit]
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions