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authorManu Gautam <mgautam@codeaurora.org>2018-01-16 16:26:58 +0530
committerKishon Vijay Abraham I <kishon@ti.com>2018-03-08 13:56:06 +0530
commit717dab9d670eb0015c40f91e105c89537abd5f6a (patch)
tree4124d20ca93a464f68aae8cecbb0249d96e075dc /tools/perf/scripts/python
parentphy: qcom-qmp: Adapt to clk_bulk_* APIs (diff)
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phy: qcom-qmp: Power-on PHY before initialization
PHY regulators which are enabled from power_on() must be ON before turning-on clocks and initializing it as part of init(). As most of the core drivers perform power_on() after init(), move PHY regulators enable to com_init() and use power_on() to only enable pipe_clk. This pipe_clk is output from PHY and some core drivers e.g. PCIe follow specific sequence after phy_init() that mandates pipe_clk to be enabled from power_on() only. On similar lines move clk_enable from init() to com_init() which executes once for multi lane PHYs. Signed-off-by: Manu Gautam <mgautam@codeaurora.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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