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| author | Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> | 2023-09-12 07:51:33 +0300 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2023-09-18 10:05:05 +0200 |
| commit | 72977f07b035e488c3f1928832a1616c6cae7278 (patch) | |
| tree | 92a8a12c2086cf0e11e90f1e5dcb71ea08ac1bbc /tools/perf/scripts/python | |
| parent | clk: renesas: rzg2l: Simplify the logic in rzg2l_mod_clock_endisable() (diff) | |
| download | linux-72977f07b035e488c3f1928832a1616c6cae7278.tar.gz linux-72977f07b035e488c3f1928832a1616c6cae7278.zip | |
clk: renesas: rzg2l: Use FIELD_GET() for PLL register fields
Use FIELD_GET() for PLL register fields. This is its purpose.
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230912045157.177966-14-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions