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| author | José Roberto de Souza <jose.souza@intel.com> | 2021-09-22 14:52:41 -0700 |
|---|---|---|
| committer | José Roberto de Souza <jose.souza@intel.com> | 2021-09-23 10:06:16 -0700 |
| commit | 73262db68c27ed25452ffd3b57e051e1791de713 (patch) | |
| tree | b8e990a6e19076ad9aaff75a73888c77524caaea /tools/perf/scripts/python | |
| parent | drm/i915/display/dmc: Set DC_STATE_DEBUG_MASK_CORES after firmware load (diff) | |
| download | linux-73262db68c27ed25452ffd3b57e051e1791de713.tar.gz linux-73262db68c27ed25452ffd3b57e051e1791de713.zip | |
drm/i915/display: Match PSR2 selective fetch sequences with specification
We were not completely following the selective fetch programming
sequence, here some things we were doing wrong:
- not programming plane selective fetch a PSR2_MAN_TRK_CTL registers
when doing a modeset
- programming PSR2_MAN_TRK_CTL out of vblank
With this changes the last remainig underrun found in Alderlake-P is
fixed.
Bspec: 55229
Tested-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Reviewed-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210922215242.66683-2-jose.souza@intel.com
Diffstat (limited to 'tools/perf/scripts/python')
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