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| author | Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com> | 2025-10-23 11:19:15 +0300 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2025-10-27 12:15:00 +0100 |
| commit | 79276fb06d2f7769613abeeed65d69013137cefb (patch) | |
| tree | d114708a31a164bb333a5b483565471d12d37f6f /tools/perf/scripts/python | |
| parent | clk: renesas: r9a09g057: Add clock and reset entries for DSI and LCDC (diff) | |
| download | linux-79276fb06d2f7769613abeeed65d69013137cefb.tar.gz linux-79276fb06d2f7769613abeeed65d69013137cefb.zip | |
clk: renesas: r9a09g077: Add TSU module clock
The Renesas RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs have a TSU
peripheral which is controlled by a module clock.
The TSU module clock is enabled in register MSTPCRD (0x30c), at bit 7,
resulting in a (0x30c - 0x300) / 4 * 100 + 7 = 307 index.
Add it to the list of module clocks.
Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20251023081925.2412325-2-cosmin-gabriel.tanislav.xa@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions