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| author | Anusha Srivatsa <anusha.srivatsa@intel.com> | 2022-11-17 15:00:02 -0800 |
|---|---|---|
| committer | Anusha Srivatsa <anusha.srivatsa@intel.com> | 2022-11-21 15:19:50 -0800 |
| commit | 86c0ef7234a7c517b010fd5ecf1e176127bce521 (patch) | |
| tree | 045520629dc6d39faf5ea8754141def934f19cdd /tools/perf/scripts/python | |
| parent | drm/i915/display: Do both crawl and squash when changing cdclk (diff) | |
| download | linux-86c0ef7234a7c517b010fd5ecf1e176127bce521.tar.gz linux-86c0ef7234a7c517b010fd5ecf1e176127bce521.zip | |
drm/i915/display: Add CDCLK Support for MTL
As per bSpec MTL has 38.4 MHz Reference clock.
Adding the cdclk tables and cdclk_funcs that MTL
will use.
v2: Revert to using bxt_get_cdclk()
BSpec: 65243
Cc: Clint Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Reviewed-by: Clint Taylor <Clinton.A.Taylor@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20221117230002.792096-3-anusha.srivatsa@intel.com
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions