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| author | Athira Rajeev <atrajeev@linux.vnet.ibm.com> | 2020-11-26 11:54:44 -0500 |
|---|---|---|
| committer | Michael Ellerman <mpe@ellerman.id.au> | 2020-12-04 01:01:29 +1100 |
| commit | 91668ab7db4bcfae332e561df1de2401f3f18553 (patch) | |
| tree | 1e7f7b45b14dd24c50d393613416d14e169e6b46 /tools/perf/scripts/python | |
| parent | powerpc/perf: Fix to update cache events with l2l3 events in power10 (diff) | |
| download | linux-91668ab7db4bcfae332e561df1de2401f3f18553.tar.gz linux-91668ab7db4bcfae332e561df1de2401f3f18553.zip | |
powerpc/perf: MMCR0 control for PMU registers under PMCC=00
PowerISA v3.1 introduces new control bit (PMCCEXT) for restricting
access to group B PMU registers in problem state when
MMCR0 PMCC=0b00. In problem state and when MMCR0 PMCC=0b00,
setting the Monitor Mode Control Register bit 54 (MMCR0 PMCCEXT),
will restrict read permission on Group B Performance Monitor
Registers (SIER, SIAR, SDAR and MMCR1). When this bit is set to zero,
group B registers will be readable. In other platforms (like power9),
the older behaviour is retained where group B PMU SPRs are readable.
Patch adds support for MMCR0 PMCCEXT bit in power10 by enabling
this bit during boot and during the PMU event enable/disable callback
functions.
Signed-off-by: Athira Rajeev <atrajeev@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/1606409684-1589-8-git-send-email-atrajeev@linux.vnet.ibm.com
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions