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| author | Sakari Ailus <sakari.ailus@linux.intel.com> | 2020-09-01 13:08:26 +0200 |
|---|---|---|
| committer | Mauro Carvalho Chehab <mchehab+huawei@kernel.org> | 2020-12-07 15:36:11 +0100 |
| commit | 9454432af0c874eba7abb1abb76bbf62950a9087 (patch) | |
| tree | 3c77bbbc30dfbe0afba1229709e3d9767c7b3318 /tools/perf/scripts/python | |
| parent | media: ccs-pll: Split limits and PLL configuration into front and back parts (diff) | |
| download | linux-9454432af0c874eba7abb1abb76bbf62950a9087.tar.gz linux-9454432af0c874eba7abb1abb76bbf62950a9087.zip | |
media: ccs-pll: Use correct VT divisor for calculating VT SYS divisor
Use the correct video timing divisor to calculate the SYS divisor. Instead
of the current value, the minimum was used. This could have resulted in a
too low SYS divisor.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions