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| author | Alexandre Ghiti <alexandre.ghiti@canonical.com> | 2021-12-06 11:46:55 +0100 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@rivosinc.com> | 2022-06-01 20:38:34 -0700 |
| commit | 9d19f2b5256ef6cdd4947b48fab4032d0060e916 (patch) | |
| tree | e9367ff01cbc4a6c422d1c59448e6dc6a292bc42 /tools/perf/scripts/python | |
| parent | RISC-V: Only default to spinwait on SBI-0.1 and M-mode (diff) | |
| download | linux-9d19f2b5256ef6cdd4947b48fab4032d0060e916.tar.gz linux-9d19f2b5256ef6cdd4947b48fab4032d0060e916.zip | |
Documentation: riscv: Add sv48 description to VM layout
sv48 was just introduced, so add its virtual memory layout to the
documentation.
Signed-off-by: Alexandre Ghiti <alexandre.ghiti@canonical.com>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions