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| author | Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> | 2023-09-29 01:07:01 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2023-10-05 14:25:00 +0200 |
| commit | 9e40584dc2592edbd35485731c3e9ab1291e6a13 (patch) | |
| tree | 115045d4523dcaa15cc58610534843917c24c012 /tools/perf/scripts/python | |
| parent | riscv: dts: renesas: r9a07g043f: Add L2 cache node (diff) | |
| download | linux-9e40584dc2592edbd35485731c3e9ab1291e6a13.tar.gz linux-9e40584dc2592edbd35485731c3e9ab1291e6a13.zip | |
riscv: dts: renesas: r9a07g043f: Add dma-noncoherent property
RZ/Five is a noncoherent SoC so to indicate this add dma-noncoherent
property to RZ/Five SoC DTSI.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230929000704.53217-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions