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| author | José Roberto de Souza <jose.souza@intel.com> | 2019-12-05 13:03:50 -0800 |
|---|---|---|
| committer | José Roberto de Souza <jose.souza@intel.com> | 2019-12-06 15:19:38 -0800 |
| commit | ad457191015a197b3daf1a259ed8e7f70bf68bb9 (patch) | |
| tree | 2915385361e26002d7e51c30dfe73766ef3b73ac /tools/perf/scripts/python | |
| parent | 3ca8f1918883796eaf48c02c50288a255f33c864 (diff) | |
| download | linux-ad457191015a197b3daf1a259ed8e7f70bf68bb9.tar.gz linux-ad457191015a197b3daf1a259ed8e7f70bf68bb9.zip | |
drm/i915/display: Refactor intel_commit_modeset_disables()
Commit 9c722e17c1b9 ("drm/i915: Disable pipes in reverse order")
reverted the order that pipes gets disabled because of TGL
master/slave relationship between transcoders in MST mode.
But as stated in a comment in skl_commit_modeset_enables() the
enabling order is not always crescent, possibly causing previously
selected slave transcoder being enabled before master so another
approach will be needed to select a transcoder to master in MST mode.
It will be similar to the approach taken in port sync.
But instead of implement something like
intel_trans_port_sync_modeset_disables() to MST lets simply it and
iterate over all pipes 2 times, the first one disabling any slave and
then disabling everything else.
The MST bits will be added in another patch.
v2:
Not using crtc->active as it is deprecated
v3:
Removing is_trans_port_sync_mode() check, just check for
is_trans_port_sync_master() is enough
v4:
Adding and using is_trans_port_sync_slave(), otherwise non-port sync
pipes will be disabled in the first loop, what is not wrong but is
not what patch description promises
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> (v2)
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20191205210350.96795-3-jose.souza@intel.com
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions
