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| author | Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> | 2025-01-09 13:50:36 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2025-02-03 11:07:05 +0100 |
| commit | b32e27f633044b1670f4cb9abe95ae43496c7ad0 (patch) | |
| tree | 11801a769ea4a9de64c3dedb034ed13f1430b20d /tools/perf/scripts/python | |
| parent | clk: renesas: r9a07g044: Add clock and reset entry for DRP-AI (diff) | |
| download | linux-b32e27f633044b1670f4cb9abe95ae43496c7ad0.tar.gz linux-b32e27f633044b1670f4cb9abe95ae43496c7ad0.zip | |
clk: renesas: r8a779a0: Add FCPVX clocks
Add the FCPVX modules clock for Renesas R-Car V3U.
Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250109125036.2399199-1-niklas.soderlund+renesas@ragnatech.se
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions