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| author | Chris Brandt <chris.brandt@renesas.com> | 2016-09-01 22:32:25 -0400 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2016-09-05 14:16:25 +0200 |
| commit | b452dfe92f651601d04d7b122d5b96e74d7ae030 (patch) | |
| tree | 5fea9e92a904098003c2d096a4383a0bcf76f487 /tools/perf/scripts/python | |
| parent | clk: renesas: r8a7796: Add SDIF clocks (diff) | |
| download | linux-b452dfe92f651601d04d7b122d5b96e74d7ae030.tar.gz linux-b452dfe92f651601d04d7b122d5b96e74d7ae030.zip | |
clk: renesas: rz: Select EXTAL vs USB clock
Check the MD_CLK pin to determine the current clock mode in order to set
the pll clock parent correctly.
Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions