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| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2017-03-29 10:05:52 +0200 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2017-05-15 09:46:31 +0200 |
| commit | b93e7eb5ed86983acece9aad8a1f82db1020d62b (patch) | |
| tree | ebd7738b7be54e0901e7a3b93ad2bb1630829f59 /tools/perf/scripts/python | |
| parent | clk: renesas: rcar-gen2: Fix PLL0 on R-Car V2H and E2 (diff) | |
| download | linux-b93e7eb5ed86983acece9aad8a1f82db1020d62b.tar.gz linux-b93e7eb5ed86983acece9aad8a1f82db1020d62b.zip | |
clk: renesas: r8a7745: Remove nonexisting scu-src[0789] clocks
RZ/G1E does not have the SCU-SRC[0789] modules and module clocks.
Fixes: 9127d54bb8947159 ("clk: renesas: cpg-mssr: Add R8A7745 support")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions