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| author | AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> | 2022-12-06 12:23:30 +0100 |
|---|---|---|
| committer | Matthias Brugger <matthias.bgg@gmail.com> | 2023-01-09 17:16:49 +0100 |
| commit | c5f30727ce68da227cfba95450a358cbd75e814c (patch) | |
| tree | c08702b99d27b4b62531bbabbeb78c5ca1e0bf22 /tools/perf/scripts/python | |
| parent | arm64: dts: mt8183: Add complete CPU caches information (diff) | |
| download | linux-c5f30727ce68da227cfba95450a358cbd75e814c.tar.gz linux-c5f30727ce68da227cfba95450a358cbd75e814c.zip | |
arm64: dts: mt6795: Add complete CPU caches information
This SoC's AP subsystem has 8x Cortex-A53 CPUs, specifically,
four CPUs per cluster, with two CPU clusters.
Each CPU has:
- A 32KB I-cache, 2-way set associative;
- A 32KB D-cache, 4-way set associative.
Each cluster has a unified 1MB L2 cache, 16-way set associative.
With that in mind, add the appropriate properties needed to specify the
caches information for this SoC, which will now be correctly exported
to sysfs.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20221206112330.78431-6-angelogioacchino.delregno@collabora.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions