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| author | Imre Deak <imre.deak@intel.com> | 2021-10-18 12:41:53 +0300 |
|---|---|---|
| committer | Imre Deak <imre.deak@intel.com> | 2021-10-20 12:20:27 +0300 |
| commit | caae4fb537d8437b9290d8a1010adfaf174b29e6 (patch) | |
| tree | e55e9b3ea23e7d31e803e451f94f8c22f210d4c7 /tools/perf/scripts/python | |
| parent | drm/i915/dp: Ensure sink/link max lane count values are always valid (diff) | |
| download | linux-caae4fb537d8437b9290d8a1010adfaf174b29e6.tar.gz linux-caae4fb537d8437b9290d8a1010adfaf174b29e6.zip | |
drm/i915/dp: Sanitize sink rate DPCD register values
If the DPCD sink rate values read from the sink are invalid, the
driver will sanitize this in intel_dp_set_common_rates(), by setting a
default 162000 link rate in common rates and printing a WARN().
WARN()s should only be triggered by bugs in the code and not by external
factors like the above (an invalid DPCD injected maliciously or read from a
buggy monitor). So fixup the invalid DPCD sink rate values already and print
an error in this case (since it's still a user visible problem).
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Acked-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211018094154.1407705-6-imre.deak@intel.com
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions