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authorHeiko Stuebner <heiko.stuebner@theobroma-systems.com>2019-12-16 13:24:47 +0100
committerKishon Vijay Abraham I <kishon@ti.com>2020-01-08 12:58:06 +0530
commitcb18b9a92b0baaa3188d67d1371079c1eacb3454 (patch)
treee6aafdaaa35b099690ec14d1d97268ecdd3458f4 /tools/perf/scripts/python
parentphy: lantiq: vrx200-pcie: Remove unneeded semicolon (diff)
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dt-bindings: phy: drop #clock-cells from rockchip,px30-dsi-dphy
Further review of the dsi components for the px30 revealed that the phy shouldn't expose the pll as clock but instead handle settings via phy parameters. As the phy binding is new and not used anywhere yet, just drop them so they don't get used. Fixes: 3817c7961179 ("dt-bindings: phy: add yaml binding for rockchip,px30-dsi-dphy") Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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