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authorChristoph Hellwig <hch@lst.de>2019-04-25 08:12:11 +0200
committerJens Axboe <axboe@kernel.dk>2019-04-25 09:11:53 -0600
commitcc6be13159316e8bdcd8bbb5209315256e151337 (patch)
treedb24e516a7edbf822c8481972e206de5947fcd95 /tools/perf/scripts/python
parentbcache: avoid potential memleak of list of journal_replay(s) in the CACHE_SYN... (diff)
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mtip32xx: remove trim support
The trim support in mtip32xx has been "temporarily" disabled for 6 years, which is 3/4 of the time the driver even exists in the tree. Remove it as it obviously is dead code now. Signed-off-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Jens Axboe <axboe@kernel.dk>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions
8-01-28 13:18:44 +0900'>2008-01-28sh: Split out extable.c _32 and _64 variants.Paul Mundt5-36/+52 2008-01-28sh: Add SH-5 support to the consistent DMA impl.Paul Mundt2-20/+30 2008-01-28sh: flush_cache_sigtramp() takes 1 arg only.Paul Mundt1-1/+1 2008-01-28sh: Move vsyscall_init() defs up one level.Paul Mundt2-6/+6 2008-01-28sh: Nopped out p3_cache_init() on SH-5 also.Paul Mundt1-0/+1 2008-01-28sh: Fix up VMALLOC_START for SH-5.Paul Mundt1-0/+4 2008-01-28sh: Move over the SH-5 head.S and tlb.h.Paul Mundt6-44/+24 2008-01-28sh: Have SH-5 provide an {en,dis}able_fpu() impl.Paul Mundt3-10/+21 2008-01-28sh: Disable initial cache flush on SH-5.Paul Mundt1-14/+18 2008-01-28sh: Don't reference UBC code in CPU init on sh64.Paul Mundt1-1/+6 2008-01-28sh: imask IRQ depends on sh32.Paul Mundt1-1/+2 2008-01-28sh: Move in the SH-5 traps.c impl.Paul Mundt4-3/+2