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| author | José Roberto de Souza <jose.souza@intel.com> | 2020-10-05 10:54:47 -0700 |
|---|---|---|
| committer | José Roberto de Souza <jose.souza@intel.com> | 2020-10-07 13:06:20 -0700 |
| commit | cf72562094a0930ea158ca6e7c4eab9c71deab2a (patch) | |
| tree | 0f9a55772269968086df3072422d8b299c009a11 /tools/perf/scripts/python | |
| parent | drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock (diff) | |
| download | linux-cf72562094a0930ea158ca6e7c4eab9c71deab2a.tar.gz linux-cf72562094a0930ea158ca6e7c4eab9c71deab2a.zip | |
drm/i915/display/ehl: Limit eDP to HBR2
Recent update in documentation defeatured eDP HBR3 for EHL and JSL.
v2:
- Remove dead code in ehl_get_combo_buf_trans()
v3:
- Rebase
BSpec: 32247
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Vidya Srinivas <vidya.srinivas@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20201005175447.93430-1-jose.souza@intel.com
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions